As shown in FIG. 1, a four-channel DC/DC PWM converter 10 comprises a control circuit 12 to manipulate a four-channel power stage 14, and each channel of the power stage 14 comprises two transistors 1404 and 1406 connected in series between an input voltage Vin and ground GND, in which the transistors 1404 and 1406 are alternatively switched by one of four modulation signals PWM[1] to PWM[4] provided by the control circuit 12, so as to produce four channel currents IO1 to IO4 respectively. The channel currents IO1 to IO4 are combined to an output current IO to charge a capacitor C to thereby produce an output voltage VO. The control circuit 12 monitors the channel currents IO1 to IO4 and the output voltage VO, in order to modulate the duty cycle of the transistors 1404 and 1406 in the power stage 14. FIG. 2 shows a circuit diagram of a conventional control circuit 12, in which a channel-current sensor 1236 senses the channel currents IO1 to IO4 to produce four current-sensing signals Ix[1] to Ix[4] respectively, a combiner 1234 combines the current-sensing signals Ix[1] to Ix[4] to produce a summing signal ISUM which flows through a resistor RADJ connected between a pin ADJ and ground GND to produce an adjusting voltage VADJ, a digital-to-analog converter (DAC) 1202 converts a digital voltage signal VID[n:0] to an analog voltage VIA, a combiner 1204 combines the analog voltage VIA with the adjusting voltage VADJ to produce a reference voltage signal Vref1, an error amplifier 1206 monitors the output voltage VO by comparing a feedback signal FB proportional to the output voltage VO with the reference voltage signal Vref1 to produce an error signal VEA, four ramp generators 1210, 1212, 1214 and 1216 generate four ramp signals RAMP[1], RAMP[2], RAMP[3] and RAMP[4] respectively under a clock CLK provided by an oscillator 1208 according to the voltage on a pin OSC, a combiner 1218 shifts the level of the ramp signal RAMP[1] by the current-sensing signal Ix[1] to produce a ramp signal RAMP[1]′, a comparator 1226 compares the error signal VEA with the ramp signal RAMP[1]′ to produce the modulation signal PWM[1] for the first channel of the power stage 14, a combiner 1220 shifts the level of the ramp signal RAMP[2] by the current-sensing signal Ix[2] to produce a ramp signal RAMP[2]′, a comparator 1228 compares the error signal VEA with the ramp signal RAMP[2]′ to produce the modulation signal PWM[2] for the second channel of the power stage 14, a combiner 1222 shifts the level of the ramp signal RAMP[3] by the current-sensing signal Ix[3] to produce a ramp signal RAMP[3]′, a comparator 1230 compares the error signal VEA with the ramp signal RAMP[3]′ to produce the modulation signal PWM[3] for the third channel of the power stage 14, a combiner 1224 shifts the level of the ramp signal RAMP[4] by the current-sensing signal Ix[4] to produce a ramp signal RAMP[4]′, a comparator 1232 compares the error signal VEA with the ramp signal RAMP[4]′ to produce the modulation signal PWM[4] for the fourth channel of the power stage 14, and a resistor ROSC is connected between the pin OSC and ground GND for setting the switching frequency of the power stage 14.
FIG. 3 shows a conventional circuit for one channel of the channel-current sensor 1236, in which a transconductive amplifier 12362 senses the channel current IO1 flowing through a sensing resistor R1, so as to produce a voltage dropVS=IO1×R1  [Eq-1]and due to the virtual short between the inputs CSP and CSN of the transconductive amplifier 12362, the voltage drop across a resistor Rx1 is equal to the voltage VS, and therefore the transconductive amplifier 12362 produces the current-sensing signalIx[1]=VS/Rx1=(IO1×R1)/Rx1   [Eq-2]
For a DC/DC PWM converter, it is very important to control the switching frequency of the transistors 1404 and 1406 in the power stage 14. FIG. 4 shows a waveform diagram of the output current IO and the output voltage VO when the transistors 1404 and 1406 are switched with low switching frequency, in which waveform 20 represents the output current IO, waveform 22 represents the adjusting voltage VADJ, waveform 24 represents the output voltage VO, and waveform 26 represents the average voltage VO(AVG) of the output voltage VO. As the load changes from light to heavy, the output current IO suddenly increases as shown by the waveform 20, the adjusting voltage VADJ also increases with the increasing output current IO as shown by the waveform 22 since it is proportional to the output current IO, the output voltage VO drops down to a lower level until the load changes from heavy back to light, and then the output voltage VO will recover to the previous level, as shown by the waveform 24. In this case, because the switching frequency is low, the power stage 14 is not easy to heat when the load is heavy, thereby having good efficiency. However, due to the low switching frequency, as shown by the waveform 26, the output voltage VO cannot keep at a predetermined level immediately when the load transient happens, and hence lower when changing from light load to heavy load and higher when changing from heavy load to light load, causing poor transient response.
FIG. 5 shows a waveform diagram of the output current IO and the output voltage VO when the transistors 1404 and 1406 are switched with high switching frequency, in which waveform 30 represents the output current IO, waveform 32 represents the adjusting voltage VADJ, waveform 34 represents the output voltage VO, and waveform 36 represents the average voltage VO(AVG) of the output voltage VO. As the load changes from light to heavy, the output current IO suddenly increases as shown by the waveform 30, the adjusting voltage VADJ also increases with the increasing output current IO as shown by the waveform 32 since it is proportional to the output current IO, the output voltage VO drops down to a lower level until the load changes from heavy back to light, and then the output voltage VO will recover to the previous level, as shown by the waveform 34. In this case, as shown by the waveform 36, because the switching frequency is high, the output voltage VO can keep at a predetermined level immediately when the load transient happens. However, the power stage 14 is easy to heat when the load is heavy, due to the high switching frequency, thereby resulting in poor efficiency, as shown by the waveform 34.
Therefore, it is desired a control circuit and method to improve both heavy load efficiency and load transient response of a DC/DC PWM converter.